1. Field of the Invention
The present invention relates to an integrated device having a plurality of memory systems including processors or other processing devices mounted thereon and sharing memories of the systems.
2. Description of the Related Art
In a system mounting a plurality of memory systems, when an architecture stressing parallel processing is employed, for example, a configuration as shown in FIG. 1 is exhibited. In the configuration of FIG. 1, since priority is given to parallel processing, logic circuits (processors) 1-1 to 1-4 and memory macros 2-1 to 2-4 are connected in one-to-one correspondence. In the configuration of FIG. 1, while logic circuits 1 and memory macros 2 are connected in one-to-one correspondence since priority is given to parallel processing, in order for logic circuits 1 to refer to data of the adjacent logics, it is necessary to use a path going through a higher device.
Therefore, in general, a configuration of directly connecting logic circuits 1 to the adjacent memories by cross bars (Xbar) 3 as shown in FIG. 2 is employed.